ECE 6745 Project 2: Accelerator Tape-Out
Accelerator RTL Design

In this project, students will leverage what they learned in the first project to transition to using a commercial standard-cell library and commercial electronic design automation tools for simulation, synthesis, place-and-route, static-timing analysis, power analysis, design rule checking (DRC), and layout-vs-schematic checking (LVS). Students will develop a simple accelerator in Verilog RTL and evaluate the potential benefit of using this accelerator in the context of a RISC-V processor. Students will then combine just their accelerator with an SPI interface and use the commercial library and tools to turn this accelerator+SPI into complete chip layout in TSMC 180nm. We have some project ideas here:

https://cornell-ece6745.github.io/ece6745-mkdocs/ece6745-project2-ideas

The project includes three parts:

Part A: Software & Testing
Part B: Accelerator RTL Milestone
Part C: Accelerator RTL Design
Part D: ASIC Evaluation
Part E: Tape-out and Report

All parts must be done in a group of 2-3 students. You can confirm your group on Canvas (Click on People, then Groups, then search for your name to find your project group).

All students must contribute to and understand all submitted work!

It is not acceptable for one student to do all of part A and a different student to do all of part B/C. It is not acceptable for one student to only focus on one module of part B/C and not understand anything about the other modules. All students must contribute and understand all aspects of all parts. The instructors will also survey the Git commit log on GitHub to confirm that all students are contributing equally. If you are using a "pair programming" style, then both students must take turns using their own account so both students have representative Git commits. Students should create commits after finishing each step of the project, so their contribution is clear in the Git commit log. It is fine for the Git commit log to indicate that a student took the lead on just one part, but the student is still responsible for reviewing and understanding all aspects included as part of the submission. A student whose contribution is limited as represented by the Git commit log will receive a significant deduction to their project score.

This handout assumes that you have read and understand the course tutorials and that you have attended the lab sections. To get started, use VS Code to log into a specific ecelinux server, use MS Remote Desktop to log into the same ecelinux server, source the setup scripts, and clone your remote repository from GitHub:

% source setup-ece6745.sh
% source setup-gui.sh
% xclock &
% mkdir -p ${HOME}/ece6745
% cd ${HOME}/ece6745
% git clone git@github.com:cornell-ece6745/project2-groupXX
% cd project2-groupXX
% tree

where XX should be replaced with your group number. You can both pull and push to your remote repository. If you have already cloned your remote repository, then use git pull to ensure you have any recent updates before working on your lab assignment.

% cd ${HOME}/ece6745/project1-groupXX
% git pull
% tree

where XX should be replaced with your group number. Your repo contains the following directories.

.
├── sim
│   ├── vc
│   ├── tut3_verilog
│   ├── lab5_xcel
│   ├── proc
│   ├── sram
│   ├── cache
│   ├── pmx
│   └── proj2
├── app
│   ├── scripts
│   ├── ece6745
│   ├── simple
│   ├── ubmark
│   └── proj2
└── asic
    ├── designs
    ├── steps
    │   └── block
    │       ├── 01-pymtl-rtlsim
    │       ├── 02-synopsys-vcs-rtlsim
    │       ├── 03-synopsys-dc-synth
    │       ├── 04-synopsys-vcs-fflgsim
    │       ├── 05-cadence-innovus-pnr
    │       ├── 06-synopsys-pt-sta
    │       ├── 07-synopsys-vcs-baglsim
    │       ├── 08-synopsys-pt-pwr
    │       ├── 09-mentor-calibre-drc
    │       ├── 10-mentor-calibre-lvs
    │       └── 11-summarize-results
    └── playground
        └── proj2
            ├── 01-pymtl-rtlsim
            ├── 02-synopsys-vcs-rtlsim
            ├── 03-synopsys-dc-synth
            ├── 04-synopsys-vcs-ffglsim
            ├── 05-cadence-innovus-pnr
            ├── 06-synopsys-pt-sta
            ├── 07-synopsys-vcs-baglsim
            ├── 08-synopsys-pt-pwr
            ├── 09-mentor-calibre-drc
            └── 10-mentor-calibre-lvs

1. Accelerator RTL Model & Testing

Finish your accelerator RTL as described in the previous part. Use the automated ASIC block flow to push your accelerator through the commercial flow to: (1) ensure your design is fully synthesizable; and (2) ensure your design will fit on the tapeout. The following steps show how to use the block flow.

% mkdir -p $HOME/ece6745/project2-groupXX/asic/build-proj2
% cd $HOME/ece6745/project2-groupXX/asic/build-proj2
% pyhflow ../designs/proj2.yml
% ./01-pymtl-rtlsim/run
% ./02-synopsys-vcs-rtlsim/run
% ./03-synopsys-dc-synth/run
% ./04-synopsys-vcs-fflgsim/run
% ./05-cadence-innovus-pnr/run
% ./06-synopsys-pt-sta/run
% ./07-synopsys-vcs-baglsim/run
% ./08-synopsys-pt-pwr/run
% ./09-mentor-calibre-drc/run
% ./10-mentor-calibre-lvs/run
% ./11-summarize-results/run

Make sure each step works without errors before moving on to the next step. Each group's chip will be 950x950um but not all of this area is available for your accelerator. There is a sealring around the outside of the chip which uses 15um. The I/O pads used to connect your chip to the package will be arranged in a ring around the outside of the chip. These I/O pads are about 100um deep, and we will need another 60um of space for the power rings. So students will only have approximately 600x600um = 360kum^2 of core area. However, we will also need to add a SPI minion and debug unit which takes up about 32kum^2 of standard cell area. Assuming a 50% density this requires approximately 60kum^2 of core area leaving a total of 300kum^2 of core area for the accelreator. The summarize results step will show both the PNR standard cell area (i.e., the area of just the standard cells) and the PNR core area (i.e., the area of the standard cells and filler cells). The PNR core area needs to be less than 300kum^2 and the density needs to be less than 70% to improve the chances of your accelerator fitting on the tapeout.

2. Project Submission

To submit your code you simply push your code to GitHub. You can push your code as many times as you like before the deadline. Students are responsible for going to the GitHub website for your repository, browsing the source code, and confirming that the code they want to submit is on GitHub. Be sure to verify your code is passing all of your simulations on ecelinux. Your submission will be assessed for code quality and functionalty. You should be continuing to improve your testing strategy.

Here is how we will be testing your final code submission for part C. First, we will clone your repo and create an environment variable for the top of your repo.

% mkdir -p ${HOME}/ece6745
% cd ${HOME}/ece6745
% git clone git@github.com:cornell-ece6745/project2-groupXX
% cd project2-groupXX
% TOPDIR=$PWD

Then, we will run your tests for your baseline software both natively, cross-compiled running on the ISA simulator, and cross-compiled running on the processor+cache RTL model.

% mkdir -p $TOPDIR/app/build-native
% cd $TOPDIR/app/build-native
% ../configure
% make proj2-baseline-test
% ./proj2-baseline-test

% mkdir -p $TOPDIR/app/build
% cd $TOPDIR/app/build
% ../configure --host=riscv64-unknown-elf
% make proj2-baseline-test
% ../../sim/pmx/pmx-sim ./proj2-baseline-test

% mkdir -p $TOPDIR/app/build
% cd $TOPDIR/app/build
% ../configure --host=riscv64-unknown-elf
% make proj2-baseline-test
% ../../sim/pmx/pmx-sim --proc-impl rtl --cache-impl rtl ./proj2-baseline-test

Then, we will run your tests for your accelerator FL and RTL models.

% mkdir -p $TOPDIR/sim/build
% cd $TOPDIR/sim/build
% pytest ../proj2/test/Proj2XcelFL_test.py
% pytest ../proj2/test/Proj2Xcel_test.py

Then, we will run your tests for your accelerator software both natively, cross-compiled running on the ISA simulator, and cross-compiled running on the processor+cache+xcel RTL model.

% mkdir -p $TOPDIR/app/build-native
% cd $TOPDIR/app/build-native
% ../configure
% make proj2-xcel-test
% ./proj2-xcel-test

% mkdir -p $TOPDIR/app/build
% cd $TOPDIR/app/build
% ../configure --host=riscv64-unknown-elf
% make proj2-xcel-test
% ../../sim/pmx/pmx-sim --xcel-impl proj2-fl ./proj2-xcel-test

% mkdir -p $TOPDIR/app/build
% cd $TOPDIR/app/build
% ../configure --host=riscv64-unknown-elf
% make proj2-xcel-test
% ../../sim/pmx/pmx-sim --proc-impl rtl --cache-impl rtl \
    --xcel-impl proj2-rtl ./proj2-xcel-test

Note that if your tests take a while to run you will need to modify the GitHub Actions workflow YAML file to increase the timeout and/or increase the --max-cycles command line option to pmx-sim.

You do not need to finalize your accelerator!

Students must submit an initial version of their accelerator but they will almost certainly continue to improve their accelerator as they push towards tape-out. The key is to get a very simple initial version of their accelerator ready for submission. It is ok if this very simple initial version of the accelerator is not optimized, or if the very simple initial version of the accelerator does not support all of the desired functionality. Start small; start simple; then you can continue to incrementally add complexity as you push towards tape-out.

ECE 6745 Project 2: Accelerator Tape-OutAccelerator RTL Design

1. Accelerator RTL Model & Testing

2. Project Submission

ECE 6745 Project 2: Accelerator Tape-Out
Accelerator RTL Design